I think that if I were to break the paper into two parts, it would be (1) We made CNFETs in industry and characterized them (actually making industry-standard 200mm wafers of CNFETs and measuring the devices) and (2) everything that went behind that to make it happen (i.e., we had to identify a way to deposit CNTs for making CNFETs that would be a good candidate for this first implementation in industry, modify the process we perform in academia to make it compatible for industry integration, understand that process, make it better (dry-cycling and ACE), and ensure that the technique will lead to performance benefits vs. silicon in the future).
I think identifying the CNT deposition process that we wanted to use in industry was the most challenging aspect of the project and also has been a major limiting factor in integrating CNFETs in industry. Just a bit of background on why choosing the right CNT deposition technique is important – it turns out that the performance of the CNFETs (characterized by the energy-delay-product, EDP, of an ultimate digital system fabricated from the CNFETs) is dictated in large part by the CNT deposition process itself, as it controls both the density and alignment of the CNTs. While prior analysis has projected that very-dense and aligned CNTs (e.g., ~200-250 aligned CNTs/µm) can realize over an order-of-magnitude benefit in EDP for digital VLSI systems compared to an identical system fabricated from silicon FETs at a comparable node, there are many technical challenges that have made realizing such CNT deposition infeasible in the past. These challenges are confounded by the need that any process must be able to be translated to a commercial fabrication facility, where additional factors such as cost, reliability, and speed are added constraints.
Rather than take the conventional approach of trying to create a radical new process for achieving the ideal CNFET which has evaded researchers for so long, we instead decided to ask a very different question: “What trade-offs exists – if any do – between performance and feasibility?” As the saying goes – perfection is often an obstacle to progress. Thus, rather than perpetually delay transferring CNFETs to industry, perpetually trying to achieve that order of magnitude benefit in EDP, is there a feasible way TODAY to realize CNFETs in industry that sacrifices a small amount of benefits (e.g., perhaps promising still a significant 5X EDP benefit rather than 10X EDP benefit) but is orders of magnitude simpler to implement?
This manuscript addresses this question, and the answer is “yes” – there is a way to realize CNFETs today that can still provide a path for meeting and exceeding the performance of existing silicon technologies without requiring re-inventing the wheel. But the proof is ultimately in the pudding – which is why we are extremely excited, as a team, to report the first integration of CNFETs within multiple commercial fabrication facilities, leveraging the exact same equipment currently fabricating silicon product wafers.
But is the job done? Of course not. Many challenges remain towards realizing a CNFET technology that meets all of the yield and performance requirements for high-performance computer. However, again, there is perhaps a slightly different question we can now ask. Do we have to solve all those challenges before CNFETs can contribute to current systems in meaningful ways? If we expand our focus, there are many opportunities to incorporate CNFETs into existing silicon systems to allow new kinds of new architectures and functionalities that would never be possible with silicon alone. Importantly, many of these benefits can be realized even given the capabilities of CNFETs that we can make today. Exploring these new functionalities is a critical – and exciting – horizon we are excited to be embarking upon.
Commercial wet processing station within the silicon commercial foundry for automatically performing all CNT incubation process steps (CNT incubation, optional dry-cycling/ACE, solvent rinses and nitrogen dry).