With the continuous size down-scaling of transistors, the severe leakage current problem is unacceptable. Some transistor technologies have been provided, such as triple-FinFET and FD-SOI technology, which have prolonged Moore’s law. However, the silicon bulk structure limits the transistor performance in small footprint.
In 2016, Desai S B et al. reported that bilayer MoS2 transistor with very short effective channel length (~1nm) exhibits excellent switching characteristics (leakage current ~ 1pA). This impressive work made us realize the potential of two-dimensional (2D) in small footprint transistor architecture. Transistors based on 2D materials naturally possess the strength of FD-SOI technology and can do better. Humans use silicon, not steel, to build modern information systems because of the exceptional Si/SiO2 interface performance. However, the transistor architectures of 2D materials are still mimicking the silicon transistor route. The present research situation drives us to explore better ways to build electronic devices which are according to the unique nature of 2D materials.
In our resent work, we conceive a tailor-made transistor architecture which can make full use of 2D materials (atomic thickness and strong photoresponse). This new 2D transistor can realize OR or AND logic gate functions, while traditional transistor technology needs at least two transistors to achieve one type logic function. The device mechanism of our 2D transistor is quite different from that of the traditional silicon transistor. 2D transistor has two working surface channels, which ensure that one single 2D transistor can realize logic function. Besides, the materials thickness and light environment can switch the logic function between OR and AND. This architecture can also be flexibly expanded to achieve in-situ memory such as logic computing and data storage convergence in the same device, which could be a potential solution to the “memory wall”. We believe that future 2D circuits can own more fantastic characteristics by designing devices and circuits according to this new device mechanism.
DOI : 10.1038/s41565-019-0462-6