In computing systems nowadays, the CPU and memory are usually separate from each other and are connected with wires or buses to transfer data, following the von Neumann architecture. While the microprocessor speed have increased significantly over the years, the improvements in memory speed and the data transfer rate have been limited. In other words, for a large percentage of the time the CPU will have to be waiting for the data to be transferred. In the big data era with increasing data-intensive computation, such limitation in data transfer throughput and the off-chip memory access could result in up to 90% of latency and energy consumption. How do we solve this problem? In-memory computing is promising because the data will be directly processed in the memory chip, which reduces the redundant data movement between the computation unit and the off-chip memory.
Ternary content-addressable memory (TCAM) is a powerful in-memory computing engine for parallel search and pattern matching. For a normal random-access memory (RAM), the input is the address and the output is the data stored in it. For a TCAM, the input is the data to search for, and the TCAM will compare the input data with the data stored in the TCAM in parallel, and return the corresponding address that shows the best match with the input data. As such, it performs the look-up table function in a single clock cycle. TCAMs have been used in commercial products such as network routers, and they are becoming highly promising for a variety of data-intensive applications related to searching and matching, such as computing at the edge of the internet, multimedia processing, big data analytics and information retrieval.
The current TCAMs based on static random-access memories (SRAMs) are limited in scale, because of the relatively high power consumption and relatively large TCAM cell size (~16 transistors per cell). Emerging resistive switching memories can be used in TCAMs instead because they are nonvolatile which reduces power consumption, and each TCAM cell only needs 2 transistors and 2 memories which decreases the cell size. Yet the resistance ratios (R-ratios) between the match and mismatch states have been reported to be around 100 or below for these TCAM cells based on emerging memories, which limits the search capacity. For a TCAM cell, the R-ratio is determined by both the memory and the transistor. We integrate the two dimensional (2D) MoS2 transistors with resistive random-access memories (RRAMs) in a 2-transistor-2-resistor (2T2R) scheme to form the TCAM cell, with each MoS2 transistor addressing and driving a RRAM. Due to the large bandgap (~2 eV) and large effective mass, monolayer molybdenum disulfide (MoS2) makes transistors with extremely low off-state leakage currents. Further, the MoS2 transistors can provide robust current control for programming the RRAMs, and allows them to be programmed to higher resistance states during reset, which can increase the R-ratio.
The fabrication of the MoS2 transistors and RRAMs is highly compatible with back-end-of-line (BEOL) metal interconnect process, and the fabrication temperature is below 200°C, except for the high-temperature MoS2 growth which can be decoupled from the other steps with a low-temperature transfer process. When we search for the data in the TCAM, the two RRAMs in a TCAM cell store one bit of data together, and the search signal is sent to the gate electrodes of the two transistors. When the TCAM cell shows a high resistance, it is in a match state. Otherwise, the TCAM cell is in a mismatch state. We achieve a very large R-ratio between the match and mismatch state of up to 8.5×105, which is comparable with SRAM-based TCAM cells, with the key advantage that our TCAM cells use far fewer transistors and use non-volatile memories.
Based on our simulation, these TCAM cells with large R-ratio can enable parallel search of massive data while maintaining enough sense margin, which can find a variety of applications involving high-throughput matching and searching in data-intensive computation. We envision that due to the low fabrication temperature and the ultrathin channel of the 2D MoS2 transistors, these TCAMs can be monolithically integrated into a three-dimensional (3D) chip with small footprint and low-energy, low-latency memory access.
Nature Electronics 2, 108-114 (2019), https://doi.org/10.1038/s41928-019-0220-7