Memory is dominating electronics in the era of data-abundant computing. Fed by our gluttony for more HD photos, videos, and data analytics, there is an escalating memory capacity need to enable our next smart mobile devices and cloud servers. Big Data, AI, and IoT are impossibilities without memory technology innovation.
However, with the abundant flow of data comes the inevitable bottleneck. Fetching data from memory to the processor and back, on our semiconductor chips, costs significant energy, and it may even be greater than the energy needed to compute the data. Therefore, there has been a sustained effort to bring the memory physically closer to the on-chip circuits that perform the computations. As Moore’s law brings us ever closer to the logical conclusion of 2-D planar circuit density scaling, further component density increase will have to leverage 3-D circuits technologies. Stacking, layer-upon-layer, memory devices and systems above our Silicon chip, is where memory-centric processing converges with 3-D circuit scaling.
However, to achieve that we must overcome a process roadblock that originated from the time when we moved from Aluminum to Copper on-chip wires, back in the late 90’s. Copper interconnect wires, surrounded by low-dielectric oxides cannot tolerate temperatures above 400oC, else copper atoms extrude into the surrounding dielectrics, compromising the reliability of the wires. Since dopant activation in Silicon typically requires temperatures well above 400oC, we have to build the Silicon devices first, followed by the interconnect metallization and dielectrics (Fig.1 (Top)). Somewhat like baking a layer cake with embedded cream layers. Hence, a cardinal rule of current semiconductor chip process technology is that Silicon and Metal Wires: Thou shalt not mix the two! At least, don’t swap the Front End (transistor) and Back End (interconnect) process order. Making Silicon transistors above the metal interconnect layers for 3-D Silicon circuits compromises the devices and wires. Hence, we are motivated to search for new low-thermal budget beyond-Silicon materials and processes for transistors and memory devices, compatible with the interconnect processing.
Our group at the National University of Singapore explores such materials and processes for Monolithic 3-D integration of memory (Fig.1 (Bottom)). We showed that a 2-D form of Transition-Metal Dichalcogenide material like Tungsten Selenide (WSe2) can be used as 2-D semiconductors to form both transistors as well as resistive-based memories. A challenge typical to many 2-D material transistor is the lower effective carrier mobility and high contact resistance; which makes them weaker than well-optimized Silicon transistors. In our work, we report on techniques to overcome the handicap at both the device level, circuit, and system levels. We show that room-temperature plasma oxidation process can boost the transistor drive performance by 10x. Combined with channel stacking, we propose the possibility of realizing highly-scaled one-transistor one-resistor (1T1R) memory cells. Please check out our work published this month: “All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration” Nature communications 10 (1), 1-12 , (2019) (doi:10.1038/s41467-019-13176-4).